SED1354 Datasheet, PDF (62/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 54
Epson Research and Development
Vancouver Design Center
7.3.5 EDO-DRAM Self-Refresh Timing
Memory
Clock
RAS#
CAS#
t1
t5
t2
Stopped for
suspend mode
t3
t4
Restarted for
active mode
Figure 7-11: EDO-DRAM Self-Refresh Timing
Table 7-11: EDO-DRAM Self-Refresh Timing
Symbol
Parameter
Min
Typ
t1
Memory clock period
25
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00)
t2
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
CAS# precharge time (REG[22h] bits [3:2] = 00)
t3
CAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
1.45 t1
0.45 t1
2 t1
1 t1
CAS# setup time (REG[22h] bits [3:2] = 00 or 10)
t4
CAS# setup time (REG[22h] bits [3:2] = 01)
RAS# precharge time (REG[22h] bits [3:2] = 00)
0.45 t1 - 2
1 t1 - 2
2 t1 - 1
t5
RAS# precharge time (REG[22h] bits [3:2] = 01)
RAS# precharge time (REG[22h] bits [3:2] = 10)
1.45 t1 - 1
1 t1 - 1
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18