SED1354 Datasheet, PDF (97/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.14 External RAMDAC Read / Write Timing
Read
t1
AB[20:0]
CS#
M/R#
DACRS[1:0]
Valid RD# Command
(depends on CPU bus)
t3
DACRD#
Page 89
t2
t4
Write
Valid WR# command
(depends on CPU bus)
DACWR#
t5
t6
Figure 7-41: Generic Bus RAMDAC Read / Write Timing
Symbol
T_BCLK
t1
t2
t3
t4
t5
t6
Table 7-30: Generic Bus RAMDAC Read / Write Timing
Bus clock period
Parameter
Min
Typ
30
AB[20:0], CS#, M/R# delay to DACRS[1:0]
DACRS[1:0] hold from AB[20:0], CS#, M/R# negated
Valid RD# command to DACRS[1:0] delay
DACRD# hold from valid RD# command negated
Valid WR# command to DACWR# delay
DACWR# pulse width low
8
3
2 T_BCLK
2.45 T_BCLK
Max
10
10
33
14
2.55 T_BCLK
Units
ns
ns
ns
ns
ns
ns
ns
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16