SED1354 Datasheet, PDF (121/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 113
RAMDAC Palette Data Register
REG[2Eh] or REG[2Fh]
RAMDAC
Data Bit 7
RAMDAC
Data Bit 6
RAMDAC
Data Bit 5
RAMDAC
Data Bit 4
RAMDAC
Data Bit 3
RAMDAC
Data Bit 2
RAMDAC
Data Bit 1
RW
RAMDAC
Data Bit 0
bits 7-0
RAMDAC Palette Data Bits [7:0]
A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0
and DACRS0 = 1 to the external RAMDAC for a palette data register access. The RAMDAC data
must be transferred directly between the system data bus and the external RAMDAC through either
data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16