SED1354 Datasheet, PDF (102/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 94
Epson Research and Development
Vancouver Design Center
HRTC/FPLINE Pulse Width Register
REG[07h]
HRTC
FPLINE
Polarity
Polarity
n/a
n/a
Select
Select
HRTC/
FPLINE
Pulse Width
Bit 3
HRTC/
FPLINE
Pulse Width
Bit 2
HRTC/
FPLINE
Pulse Width
Bit 1
RW
HRTC/
FPLINE
Pulse Width
Bit 0
bit 7
HRTC Polarity Select
For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active
high. When this bit = 0, the HRTC pulse is active low.
bit 6
FPLINE Polarity Select
This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the
FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the
FPLINE pulse is active low for TFT and active high for passive LCD.
FPLINE Polarity Select
0
1
Table 8-4: FPLINE Polarity Selection
Passive LCD FPLINE Polarity
active high
active low
TFT FPLINE Polarity
active low
active high
bits 3-0
HRTC/FPLINE Pulse Width Bits [3:0]
For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For pas-
sive LCDs, FPLINE is automatically created and these bits have no effect.
HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) × 8.
The maximum HRTC pulse width is 128 pixels.
Note
This register must be programmed such that
(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Vertical Display Height Register 0
REG[08h]
Vertical
Display
Height Bit 7
Vertical
Display
Height Bit 6
Vertical
Display
Height Bit 5
Vertical
Display
Height Bit 4
Vertical
Display
Height Bit 3
Vertical
Display
Height Bit 2
Vertical
Display
Height Bit 1
RW
Vertical
Display
Height Bit 0
Vertical Display Height Register 1
REG[09h]
RW
Vertical
Vertical
n/a
n/a
n/a
n/a
n/a
n/a
Display
Display
Height Bit 9 Height Bit 8
REG[08h] bits 7-0
REG[09h] bits 1-0
Vertical Display Height Bits [9:0]
These bits specify the LCD panel and/or the CRT vertical display height, in 1-line resolution. For a
dual LCD panel only configuration, this register should be programmed to half the panel size.
Vertical display height in number of lines = (ContentsOfThisRegister) + 1.
The maximum vertical display height is 1024 lines.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18