SED1354 Datasheet, PDF (177/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Table 6-4: Related register data for Simultaneous Display
Register ^{640X480@75Hz 640X480@60Hz}
PCLK=40.0MHz
PCLK=40.0MHz
REG[04h] 0100 1111 0100 1111
REG[05h] 0001 1101 0001 0011
REG[06h] 0000 0011 0000 0001
REG[07h] 0000 0111 0000 1011
REG[08h] 1000 1111 1101 1111
REG[09h] 0000 0001 0000 0001
REG[0Ah] 0010 1100 0010 1100
REG[0Bh] 0000 0000 0000 1001
REG[0Ch] 1000 0010 0000 0001
REG[0Dh] 0000 1111 0000 1111
REG[19h] 0000 0000 0000 0000
REG[24h] 0000 0000 0000 0000
REG[26h]
REG[27h] 0000 0000 0000 0000
REG[2Ch]
program
RAMDAC
program
RAMDAC
REG[2Eh]
Notes
set horizontal display width
set horizontal non-display period
set HSYNC start position
set HSYNC polarity and pulse width
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set VSYNC start position
set VSYNC polarity and pulse width
set 8 bpp and CRT enable
set MCLK and PCLK divide
set look-up table address to 0
load look-up table
set look-up table to bank 0
set write mode address to 0
load RAMDAC palette data
Page 37
Programming Notes and Examples
Issue Date: 98/10/28
SED1354
X19A-G-002-06