SED1354 Datasheet, PDF (89/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.11 Dual Color 16-Bit Panel Timing
Page 81
FPFRAME
FPLINE
MOD
UD[7:0], LD[7:0]
VDP
VNDP
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241 LINE 2/242
FPLINE
MOD
FPSHIFT
UD7, LD7
UD6, LD6
UD5, LD5
UD4, LD4
UD3, LD3
UD2, LD2
UD1, LD1
UD0, LD0
1-R1,
1-B3,
241-R1 241-B 3
1-G1,
1-R4,
241-G 1 241-R4
1-B1,
1-G4,
241-B1 241-G4
1-R2,
1-B4,
241-R2 241-B 4
1-G2,
1-R5,
241-G 2 241-R5
1-B2,
1-G5,
241-B2 241-G5
1-R3,
1 -B 5,
241-R3 241-B 5
1-G3,
1-R6,
241-G 3 241-R6
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HDP
HNDP
1-G 638,
241-G638
1 -B 63 8,
24 1- B 638
1 -R 6 3 9 ,
241-R639
1-G 639,
241-G639
1 -B 63 9 ,
241-B639
1-R640,
241-R640
1 -G 6 4 0 ,
241-G640
1 -B 64 0 ,
241-B640
Figure 7-35: Dual Color 16-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16