SED1354 Datasheet, PDF (101/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 93
Horizontal Display Width Register
REG[04h]
Horizontal Horizontal
n/a
Display
Display
Width Bit 6 Width Bit 5
Horizontal
Display
Width Bit 4
Horizontal
Display
Width Bit 3
Horizontal
Display
Width Bit 2
Horizontal
Display
Width Bit 1
RW
Horizontal
Display
Width Bit 0
bits 6-0
Horizontal Display Width Bits [6:0]
These bits specify the LCD panel and/or the CRT horizontal display width as follows.
Contents of this Register = (Horizontal Display Width ÷ 8) - 1
For passive LCD panels the Horizontal Display Width must be divisible by 16, and for TFT LCD
panels/CRTs the Horizontal Display Width must be divisible by 8. The maximum horizontal dis-
play width is 1024 pixels.
Note
This register must be programmed such that REG[04h] ≥ 3 (32 pixels)
Horizontal Non-Display Period Register
REG[05h]
Horizontal
n/a
n/a
n/a
Non-Display
Period Bit 4
Horizontal
Non-Display
Period Bit 3
Horizontal
Non-Display
Period Bit 2
Horizontal
Non-Display
Period Bit 1
RW
Horizontal
Non-Display
Period Bit 0
bits 4-0
Horizontal Non-Display Period Bits [4:0]
These bits specify the horizontal non-display period width in 8-pixel resolution as follows.
Contents of this Register = (Horizontal Non-Display Period ÷ 8) - 1
The minimum value which should be programmed into this register is 3 (32 pixels). The maximum
value which can be programmed into this register is 1F, which gives a horizontal non-display period
width of 256 pixels.
Note
This register must be programmed such that
REG[05h] ≥ 3 and (REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
HRTC/FPLINE Start Position Register
REG[06h]
n/a
n/a
n/a
RW
HRTC/
HRTC/
HRTC/
HRTC/
HRTC/
FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start
Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0
bits 4-0
HRTC/FPLINE Start Position Bits [4:0]
For CRTs and TFTs, these bits specify the delay from the start of the horizontal non-display period
to the leading edge of the HRTC pulse and FPLINE pulse respectively.
Contents of this Register = (HRTC/FPLINE Start Position ÷ 8) - 1
The maximum HRTC start delay is 256 pixels.
Note
This register must be programmed such that
(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16