SED1354 Datasheet, PDF (80/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 72
Epson Research and Development
Vancouver Design Center
Sync Timing
FPFRAME
FPLINE
t1
t2
t3
t4
Data Timing
FPLINE
t5a
t5b
t8a
t6
t9
t7
t10 t11
FPSHIFT
t8b
FPSHIFT2
UD[3:0]
LD[3:0]
t12 t13
1
2
Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
Parameter
Min
Typ
t1 FPFRAME setup to FPLINE falling edge
note 2
t2 FPFRAME hold from FPLINE falling edge
9
t3 _{FPLINE pulse width}
9
t4 FPLINE period
note 3
t5a FPSHIFT2 falling edge to FPLINE rising edge
note 4
t5b _{FPSHIFT falling edge to FPLINE rising edge}
note 5
t6 FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge
t14 + 2
t7 FPSHIFT2, FPSHIFT period
4
t8a _{FPSHIFT falling edge to FPLINE falling edge}
note 6
t8b FPSHIFT2 falling edge to FPLINE falling edge
note 7
t9 FPLINE falling edge to FPSHIFT rising edge
18
t10 _{FPSHIFT2, FPSHIFT pulse width high}
2
t11 FPSHIFT2, FPSHIFT pulse width low
2
t12 UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
1
t13 _{UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge}
1
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1_min = t4_min - 9Ts
3. t4_min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
4. t5_min = [((REG[05h] bits [4:0]) + 1)*8 - 27]+T11 Ts
5. t5_min = [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
6. t8_min = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
7. t8_min = [((REG[05h] bits [4:0]) + 1)*8 - 18]+T11 Ts
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18