SED1354 Datasheet, PDF (317/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 17
3.1.2 Bus Interface Timing
Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for
complete bus timing details.
Note
A four-position DIP switch located on the SDU1354-D9000 allows for the following configura-
tions.
SW4
x
x
Table 3-4: DIP Switch Configuration
SW3
0
SW2
0
SW1
0
0
0
1
x
0
1
0
x
0
1
1
0
x
x
x
1
x
x
x
Where 1 = closed/on and 0 = open/off
Function
SH-3 Bus Interface
MC68K Bus
1 Interface
MC68K Bus
2 Interface
Generic Bus Interface
WAIT# - active low
WAIT# - active high
3.1.3 Memory Address (CS#, M/R#) Decode
The SED1354 is a memory-mapped device for both the registers and display buffer access. The
specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space
requirements are:
• a 2M byte linear address range for the display buffer
• 47 bytes for the registers.
3.1.4 Makefpga file
Modifications to the makefpga file to accommodate the SED1354 are:
1. Bus model: this may differ depending on processor as far as interface requirements (signal def-
initions). Epson will provide this information for each given processor interface.
2. Memory location: the system designer must determine the appropriate memory addresses for
the display buffer and register requirements.
3.2 Board Dimensions
To obtain the required number of interface signals, the SDU1354-D9000 utilizes two SmallTypeZ
slots (6 and 7). Board dimensions are 2.65x3.20 with both the CRT and LCD connectors accessible
on the outside edge.
3.3 Support Documentation Notes
Note that some files and/or documentation may refer to the SDU1354-D9000 as the SDU1354-
D9100.
Evaluation Board User Manual
Issue Date: 98/10/29
SDU1354-D9000
X19A-G-003-04