SED1354 Datasheet, PDF (45/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 37
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t15
t16
Table 7-1: SH-3 Interface Timing
Parameter
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], M/R#, RD/WR# setup to CKIO
A[20:0], M/R#, RD/WR# hold from CS#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to D[15:0] driven
Rising edge CSn# to WAIT# tri-state
Falling edge CSn# to WAIT# driven
CKIO to WAIT# delay
D[15:0] setup to first CKIO after BS# (write cycle)
D[15:0] hold (write cycle)
D[15:0] valid to WAIT# rising edge (read cycle)
Rising edge RD# to D[15:0] tri-state (read cycle)
Min Max Units
25
ns
5
ns
5
ns
4
ns
0
ns
3
ns
0
ns
0
ns
3
ns
0
4
ns
1
11
ns
3
15
ns
0
ns
0
ns
0
ns
2
9
ns
1. If the SED1354 host interface is disabled, the timing for WAIT# driven is relative to the falling
edge of CSn# or the first positive edge of CKIO after A[20:0] and M/R# become valid,
whichever occurs later.
2. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of RD# or the first positive edge of CKIO after A[20:0] and M/R# become valid,
whichever occurs later.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16