SED1354 Datasheet, PDF (362/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 10
Epson Research and Development
Vancouver Design Center
3 SED1354 Host Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to
interface to the VR4102 microprocessor. The Generic MPU host bus interface is the least
processor-specific interface mode supported by the SED1354 and was chosen to implement
this interface due to the simplicity of its timing.
The Generic MPU host bus interface is selected by the SED1354 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh]) will be set to logic ‘1’, meaning that the SED1354 will not respond to any
host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new
hardware design, this can sometimes give the appearance that the interface is not work-
ing, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354
Pin Names
AB[20:1]
AB0
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Generic MPU
A[20:1]
A0
D[15:0]
WE1#
External Decode
External Decode
BCLK
Connect to IO V_DD
RD1#
RD0#
WE0#
WAIT#
RESET#
SED1354
X19A-G-007-06
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/03/10