M16C6NK Datasheet, PDF (95/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
8. Clock Generating Circuit
Table 8.8 Allowed Transition and Setting ⁽⁹⁾
State after transition
High-Speed Mode, _{Low-Speed Low Power PLL Operation On-chip Oscillator} On-chip Oscillator
Medium-Speed
Mode
Mode ⁽²⁾
Dissipation Mode Mode (2)
Low Power
Mode _{Dissipation Mode}
High-Speed Mode,
(NOTE 8) (9) ⁽⁷⁾
-
(13) ⁽³⁾
(15)
-
Medium-Speed Mode
Low-Speed
Mode ⁽²⁾
(8)
(11) ^{(1) (6)}
-
-
-
Low Power
-
(10)
Dissipation Mode
-
-
-
PLL Operation
Mode ⁽²⁾
(12) ⁽³⁾
-
-
-
-
On-chip Oscillator
(14) ⁽⁴⁾
-
-
-
(NOTE 8) (11) ⁽¹⁾
Mode
On-chip Oscillator Low
-
-
-
-
(10) (NOTE 8)
Power Dissipation Mode
Stop Mode
(18) ⁽⁵⁾
(18)
(18)
-
(18) ⁽⁵⁾
(18) ⁽⁵⁾
Stop
Mode
(16) ⁽¹⁾
(16) ⁽¹⁾
(16) ⁽¹⁾
-
(16) ⁽¹⁾
(16) ⁽¹⁾
Wait
Mode
(17)
(17)
(17)
-
(17)
(17)
-
Wait Mode
(18)
(18)
(18)
-
(18)
(18)
-
-: Cannot transit
NOTES:
1. Avoid making a transition when the CM20 bit = 1 (oscillation stop, re-
oscillation detection function enabled). Set the CM20 bit to “0” (oscillation
stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this
mode, the on-chip oscillator can be used as peripheral function clock. Sub
clock oscillates and stops in PLL operation mode. In this mode, sub clock
can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed
mode.
4. Set the CM06 bit to “1” (divide-by-8 mode) before transiting from on-chip
oscillator mode to high- or medium-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (divide-by-8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1”
(divide-by-8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or sub
clock oscillation turned on or off) are shown in the table below.
Sub Clock Oscillating
Sub Clock Turned Off
No Divide- Divide- Divide- Divide- No Divide- Divide- Divide- Divide-
Division by-2 by-4 by-8 by-16 Division by-2 by-4 by-8 by-16
No Division
(4) (5) (7) (6) (1) - - - -
Divide-by-2 (3)
(5) (7) (6) - (1) - - -
Divide-by-4 (3) (4)
(7) (6) - - (1) - -
Divide-by-8 (3) (4) (5)
(6) - - - (1) -
Divide-by-16 (3) (4) (5) (7)
- - - - (1)
No Division (2) - - - -
(4) (5) (7) (6)
Divide-by-2 - (2) - - - (3)
(5) (7) (6)
Divide-by-4 - - (2) - - (3) (4)
(7) (6)
Divide-by-8 - - - (2) - (3) (4) (5)
(6)
Divide-by-16 - - - - (2) (3) (4) (5) (7)
9. ( ):setting method. See right table.
Setting
Operation
(1) CM04=0
Sub clock turned off
(2) CM04=1
Sub clock oscillating
(3) CM06=0
CPU clock no division
CM17=0
mode
CM16=0
(4) CM06=0
CM17=0
CPU clock divide-by-2
mode
CM16=1
(5) CM06=0
CM17=1
CPU clock divide-by-4
mode
CM16=0
(6) CM06=0
CM17=1
CPU clock divide-by-16
mode
CM16=1
(7) CM06=1
CPU clock divide-by-8 mode
(8) CM07=0
Main clock, PLL clock
or on-chip oscillator
clock selected
(9) CM07=1
Sub clock selected
(10) CM05=0
Main clock oscillating
(11) CM05=1
Main clock turned off
(12) PLC07=0
CM11=0
Main clock selected
(13) PLC07=1
CM11=1
PLL clock selected
(14) CM21=0
Main clock or
PLL clock selected
(15) CM21=1
On-chip oscillator clock
selected
(16) CM10=1
Transition to stop mode
(17) WAIT
Transition to wait mode
instruction
(18) Hardware
interrupt
Exit stop mode or wait
mode
CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
CM20, CM21
: Bits in CM2 register
PLC07
: Bit in PLC0 register
Rev.2.00 Nov 28, 2005 page 77 of 378
REJ09B0124-0200