M16C6NK Datasheet, PDF (316/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
22. Electric Characteristics (Normal-ver.)
Table 22.8 Flash Memory Version Electrical Characteristics ⁽¹⁾
Symbol
Parameter
-
Program and Erase Endurance ⁽²⁾
Standard
Unit
Min.
Typ.
Max.
100
cycle
-
Word Program Time (VCC = 5.0V)
25
200
µs
-
Lock Bit Program Time
25
200
µs
-
Block Erase Time
4-Kbyte block
0.3
4
s
(VCC = 5.0V)
8-Kbyte block
0.3
4
s
32-Kbyte block
0.5
4
s
64-Kbyte block
-
Erase All Unlocked Blocks Time
tps
Flash Memory Circuit Stabilization Wait Time
0.8
4
s
4 ✕ n ⁽³⁾
s
15
µs
NOTES:
1. Referenced to VCC = 4.5 to 5.5V, 3.0 to 3.6V, Topr = 0 to 60°C unless otherwise specified.
2. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n = 100), each block can be erased n times.
For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different address,
this counts as one program and erase endurance. Data cannot be written to the same address more than
once without erasing the block. (Rewrite prohibited)
3. n denotes the number of blocks to erase.
Table 22.9 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60°C)
Flash Program, Erase Voltage
Flash Read Operation Voltage
VCC = 3.3 ± 0.3V or 5.0 ± 0.5V
VCC = 3.0 to 5.5V
Table 22.10 Power Supply Circuit Timing Characteristics
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min. Typ. Max.
td(P-R) Time for Internal Power Supply Stabilization During Powering-On VCC = 3.0 to 5.5V
2 ms
td(R-S)
td(W-S)
STOP Release Time
Low Power Dissipation Mode Wait Mode Release Time
150 µs
150 µs
td(P-R)
Time for Internal Power Supply
Stabilization During Powering-On
VCC
CPU clock
td(P-R)
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
CPU clock
Figure 22.2 Power Supply Circuit Timing Diagram
Rev.2.00 Nov 28, 2005 page 298 of 378
REJ09B0124-0200
(a)
td(R-S)
(b)
td(W-S)