M16C6NK Datasheet, PDF (197/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8(ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
(2) IICM2 = 0, CKPH = 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
SCLi
6th bit
7th bit
Transfer to UiRB register
b15
b9 b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
8th bit
9th bit
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8(ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9 b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8(ACK, NACK)
Receive interrupt _{Transmit interrupt}
(DMA1 request)
(4) IICM2 = 1, CKPH = 1
1st bit
2nd bit
3rd bit
4th bit
SCLi
5th bit
6th bit
Transfer to UiRB register
7th bit
8th bit
b15
9th bit
b9 b8 b7
b0
D0
D7 D6 D5 D4 D3 D2 D1
UiRB register
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to UiRB register Transfer to UiRB register
i = 0 to 2
b15
b9 b8 b7
b0
b15
b9 b8 b7
b0
D0
D7 D6 D5 D4 D3 D2 D1
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
UiRB register
This diagram applies to the case where the following condition is met.
The CKDIR bit in the UiMR register = 0 (slave selected)
Figure 15.24 Transfer to UiRB Register and Interrupt Timing
Rev.2.00 Nov 28, 2005 page 179 of 378
REJ09B0124-0200