M16C6NK Datasheet, PDF (195/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
Table 15.11 Registers to Be Used and Settings in I²C Mode
Register
UiTB ⁽¹⁾
UiRB ⁽¹⁾
UiBRG
UiMR ⁽¹⁾
UiC0
UiC1
UiSMR
Bit
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS ⁽²⁾
U2RRM ⁽²⁾,
UiLCH, UiERE
IICM
ABC
UiSMR2
BBS
3 to 7
IICM2
CSC
SWC
ALS
STAC
UiSMR3
UiSMR4
SWC2
SDHI
7
0, 2, 4 and NODC
CKPH
DL2 to DL0
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR0
UCON
IFSR06, ISFR07
U0IRS, U1IRS
Function
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Invalid
Overrun error flag
Set a transfer rate
Invalid
Set to “010b”
Set to “0”
Set to “1”
Set to “0”
Select the count source for the UiBRG register Invalid
Invalid because the CRD bit = 1
Transmit register empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Slave
Set to “1”
Select the timing at which arbitration-lost Invalid
is detected
Bus busy flag
Set to “0”
See Table 15.12 I²C Mode Functions
Set this bit to “1” to enable clock synchronization Set to “0”
Set this bit to “1” to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock
Set this bit to “1” to have SDAi output
Set to “0”
stopped when arbitration-lost is detected
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
Set to “0”
See Table 15.12 I²C Mode Functions
Set the amount of SDAi digital delay
Set this bit to “1” to generate start condition Set to “0”
Set this bit to “1” to generate restart condition Set to “0”
Set this bit to “1” to generate stop condition Set to “0”
Set this bit to “1” to output each condition
Set to “0”
Select ACK or NACK
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCLi output
Set to “0”
stopped when stop condition is detected
Set to “0”
Set this bit to “1” to set the SCLi to “L” hold
at the falling edge of the 9th bit of clock
Set to “1”
Invalid
2 to 7
Set to “0”
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in I²C mode.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON
register.
Rev.2.00 Nov 28, 2005 page 177 of 378
REJ09B0124-0200