M16C6NK Datasheet, PDF (223/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
16. A/D Converter
A/D Control Register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON2
Address
03D4h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
SMP
A/D Conversion Method 0 : Without sample and hold
Select Bit
1 : With sample and hold
RW
ADGSEL0
b2 b1
0 0 : Port P10 group is selected
RW
A/D Input Group Select Bit ^{0 1 : Do not set a value}
ADGSEL1
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
RW
-
(b3)
Reserved Bit
Set to "0"
RW
CKS2
Frequency Select Bit 2 ⁽²⁾
0 : Selects fAD, divide-by-2 of fAD, or
divide-by-4 of fAD.
1 : Selects divide-by-3 of fAD, divide-by-6
RW
of fAD, or divide-by-12 of fAD.
-
(b7-b5)
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. The φAD frequency must be 10 MHz or less. The selected φAD frequency is determined by a combination of the
CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2 CKS1 CKS0
φAD
0
0
0 Divide-by-4 of fAD
0
0
1 Divide-by-2 of fAD
0
1
0
fAD
0
1
1
1
0
0 Divide-by-12 of fAD
1
0
1 Divide-by-6 of fAD
1
1
0
Divide-by-3 of fAD
1
1
1
A/D Register i (i = 0 to 7)
(b15)
b7
(b8)
b0 b7
Symbol
Address
After Reset
AD0
03C1h to 03C0h
Indeterminate
AD1
03C3h to 03C2h
Indeterminate
AD2
03C5h to 03C4h
Indeterminate
AD3
03C7h to 03C6h
Indeterminate
AD4
03C9h to 03C8h
Indeterminate
b0
AD5
03CBh to 03CAh
Indeterminate
AD6
03CDh to 03CCh
Indeterminate
AD7
03CFh to 03CEh
Indeterminate
Function
When BITS bit in ADCON1
register is "1" (10-bit mode)
When BITS bit is "0"
RW
(8-bit mode)
Low-order 8 bits of
A/D conversion result
A/D conversion result
RO
High-order 2 bits of
A/D conversion result
When read, the content is
indeterminate.
RO
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
Figure 16.3 ADCON2 Register, and AD0 to AD7 Registers
Rev.2.00 Nov 28, 2005 page 205 of 378
REJ09B0124-0200