M16C6NK Datasheet, PDF (180/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
(1) Example of Transmit Timing (when internal clock is selected)
TC
Transfer clock
TE bit in
UiC1 register
"1"
"0"
Write data to the UiTB register
TI bit in
"1"
UiC1 register
"0"
"H"
CTSi
"L"
Transferred from the UiTB register to the UARTi transmit register
TCLK
Stopped pulsing because CTSi = H
Stopped pulsing because the TE bit = 0
CLKi
TXDi
TXEPT bit in
"1"
UiC0 register
"0"
IR bit in
"1"
SiTIC register
"0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" when interrupt request is accepted, or set to "0" in a program
TC = TCLK= 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to the UiBRG register
i = 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
CKDIR bit in UiMR register = 0 (internal clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit in UiC0 register = 0 (CTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Receive Timing (when external clock is selected)
RE bit in
"1"
UiC1 register
"0"
TE bit in
UiC1 register
TI bit in
UiC1 register
RTSi
CLKi
RXDi
RI bit in
UiC1 register
"1"
"0"
Write dummy data to the UiTB register
"1"
"0"
Transferred from the UiTB register to the UARTi transmit register
"H"
Even if the reception is completed, the RTS
"L"
does not change. The RTS becomes "L"
1 / fEXT
when the RI bit changes to "0" from "1".
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Transferred from UARTi receive register
"1"
to the UiRB register
"0"
Read out from the UiRB register
IR bit in
"1"
SiRIC register _"0"
Set to "0" when interrupt request is
accepted, or set to "0" in a program
The above timing diagram applies to the case where the register bits are set
as follows:
CKDIR bit in UiMR register = 1 (external clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
TE bit in UiC1 register = 1 (transmission enabled)
RE bit in UiC1 register = 1 (reception enabled)
Write dummy data to the UiTB register
Figure 15.11 Transmit and Receive Operation
Rev.2.00 Nov 28, 2005 page 162 of 378
REJ09B0124-0200