M16C6NK Datasheet, PDF (55/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Reset
5.2 Software Reset
The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1”
(microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector.
Set the PM03 bit to “1” while the main clock is selected as the CPU clock and the main clock oscillation is stable.
In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special Function
Register (SFR) for details.
Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.
5.3 Watchdog Timer Reset
The microcomputer resets pins, the CPU and SFR when the PM12 bit in the PM1 register is set to “1” (reset
when watchdog timer underflows) and the watchdog timer underflows. Then the microcomputer executes
the program in an address determined by the reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special
Function Register (SFR) for details.
Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.
5.4 Oscillation Stop Detection Reset
The microcomputer resets and stops pins, the CPU and SFR when the CM27 bit in the CM2 register is “0”
(reset at oscillation stop, re-oscillation detection), if it detects main clock oscillation circuit stop. Refer to 8.5
Oscillation Stop and Re-Oscillation Detection Function for details.
In the oscillation stop detection reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special
Function Register (SFR) for details.
Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.
5.5 Internal Space
Figure 5.3 shows CPU register status after reset. Refer to 4. Special Function Register (SFR) for SFR
states after reset.
b15
0000h
0000h
0000h
0000h
0000h
0000h
0000h
b0
Data Register (R0)
Data Register (R1)
Data Register (R2)
Data Register (R3)
Address Register (A0)
Address Register (A1)
Frame Base Register (FB)
b19
b0
00000h
Content of addresses FFFFEh to FFFFCh
Interrupt Table Register (INTB)
Program Counter (PC)
b15
0000h
0000h
0000h
b0
User Stack Pointer (USP)
Interrupt Stack Pointer (ISP)
Static Base Register (SB)
b15
0000h
b0
Flag Register (FLG)
b15
b8 b7
b0
IPL
U I OBSZ DC
Figure 5.3 CPU Register Status After Reset
Rev.2.00 Nov 28, 2005 page 37 of 378
REJ09B0124-0200