M16C6NK Datasheet, PDF (131/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
13. Timers
13. Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as
either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer
operations as counting, reloading, etc.
Figures 13.1 and 13.2 show block diagrams of Timer A and Timer B configuration, respectively.
Main clock
PLL clock
f1
On-chip
oscillator clock
f2 ^{PCLK0 = 0}
1/2
PCLK0 = 1
1/8
1/4
f1 or f2
f8
f32
Clock prescaler
XCIN
1/32
Set the CPSR bit in the
CPSRF register to "1"
(prescaler reset)
Reset
fC32
f1 or f2 f8 f32 fC32
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
TCK1 to TCK0
00
01
10
11
Noise
filter
TCK1 to TCK0
00
01
10
11
Noise
filter
TCK1 to TCK0
00
01
10
11
Noise
filter
TCK1 to TCK0
00
01
10
11
Noise
filter
TCK1 to TCK0
00
01
10
11
Noise
filter
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
10
11 : Pulse width measuring mode
01
00
01: Event counter mode
11 _{TA0TGH to TA0TGL}
Timer A0
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
10
11 : Pulse width measuring mode
01
00
01: Event counter mode
11 _{TA1TGH t0 TA1TGL}
Timer A1
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
10
11 : Pulse width measuring mode
01
00
01: Event counter mode
11 _{TA2TGH to TA2TGL}
Timer A2
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
10
11 : Pulse width measuring mode
01
00
01: Event counter mode
11 _{TA3TGH to TA3TGL}
Timer A3
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
10
11 : Pulse width measuring mode
01
00
01: Event counter mode
11 _{TA4TGH to TA4TGL}
Timer A4
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B2 overflow or underflow
PCLK0: Bit in PCLKR register
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TAiMR register (i = 0 to 4)
TAiTGH to TAiTGL: Bits in ONSF register or TRGSR register
NOTE:
1. Be aware that TA0IN shares the pin with RXD2, SCL2 and TB5IN.
Figure 13.1 Timer A Configuration
Rev.2.00 Nov 28, 2005 page 113 of 378
REJ09B0124-0200