M16C6NK Datasheet, PDF (64/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
7. Bus
7.2 Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
7.2.1 Address Bus
The address bus consists of 20 lines, A0 to A19.
The address bus width can be chosen to be 12,
16 or 20 bits by using the PM06 bit in the PM0
register and the PM11 bit in the PM1 register.
Table 7.2 shows the PM06 and PM11 bits set
Table 7.2 PM06 and PM11 Bits Set Value and
Address Bus Width
Set Value ⁽¹⁾ Pin Function Address Bus Width
PM11 = 1 P3_4 to P3_7 12 bits
PM06 = 1 P4_0 to P4_3
PM11 = 0 A12 to A15 16 bits
values and address bus widths.
PM06 = 1 P4_0 to P4_3
When processor mode is changed from single-chip
mode to memory expansion mode, the address
bus is indeterminate until any external area is
accessed.
PM11 = 0 A12 to A15 20 bits
PM06 = 0 A16 to A19
NOTE:
1. No values other than those shown above can
7.2.2 Data Bus
be set.
When input on the BYTE pin is high (data bus is an 8-bit width), 8 lines D0 to D7 comprise the data bus;
when input on the BYTE pin is low (data bus is a 16-bit width), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
7.2.3 Chip Select Signal
_____
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The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These
_____
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 7.1 shows the CSR register.
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During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
from the CSi pin.
______
Figure 7.2 shows the example of address bus and CSi signal output.
Chip Select Control Register ⁽⁴⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSR
Address
0008h
After Reset
00000001b
Bit Symbol
Bit Name
Function
RW
CS0
CS0 Output Enable Bit 0 : Chip select output disabled RW
CS1
CS1 Output Enable Bit
(functions as I/O port)
RW
1 : Chip select output enabled
CS2
CS2 Output Enable Bit
RW
CS3
CS3 Output Enable Bit
RW
CS0W
CS1W
CS0 Wait Bit
CS1 Wait Bit
0 : With wait state
RW
1 : Without wait state ^{(1) (2) (3)}
RW
CS2W CS2 Wait Bit
RW
CS3W CS3 Wait Bit
RW
NOTES:
1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplexed bus is used, set the
CSiW bit to "0" (Wait state).
2. If the PM17 bit in the PM1 register is set to "1" (with wait state), set the CSiW bit to "0" (with wait state).
3. When the CSiW bit = 0 (with wait state), the number of wait states (in terms of clock cycles) can be selected
using the CSEi1W to CSEi0W bits in the CSE register.
4. Not available this register in T/V-ver..
Figure 7.1 CSR Register
Rev.2.00 Nov 28, 2005 page 46 of 378
REJ09B0124-0200