M16C6NK Datasheet, PDF (110/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
10. Interrupt
10.5.8 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction.
10.5.9 Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt request that has the highest priority is accepted.
For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using
the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their
interrupt priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.9
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
High
NMI
DBC
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
Peripheral Function
Single Step
Address Match
Low
Figure 10.9 Hardware Interrupt Priority
10.5.10 Interrupt Priority Resolution Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 10.10 shows the circuit that judges the interrupt priority level.
Rev.2.00 Nov 28, 2005 page 92 of 378
REJ09B0124-0200