M16C6NK Datasheet, PDF (400/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual
Rev. Date
2.00 Nov. 28, 2005
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Description
Summary
12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.2.
________
12.1.4 Effect of RDY Signal is added.
Table 12.2 DMA Transfer Cycles is revised.
Table 12.3 Coefficient j, k is revised.
12.5 Channel Priority and DMA Transfer Timing: Last sentence (Refer to ...) is added.
Figure 13.12 TA0MR to TA4MR Registers in PWM Mode: b2 is revised from “1” to “(blank)”.
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.
Figure 14.2 INVC0 Register: NOTES 5 and 6 are revised.
Figure 15.5 U0BRG to U2BRG Registers (lower): NOTE 3 is added.
Figure 15.6 U0C0 to U2C0 Registers (lower): NOTE 5 is added.
Table 15.9 Example of Bit Rates and Settings: 20 MHz and NOTE 1 are added.
Figure 15.37 SiC Register (upper): NOTE 7 is added.
Figure 15.37 SiBRG Register (middle): NOTE 4 is added.
Figure 16.1 A/D Converter Block Diagram
• ADGSEL1 to ADGSEL0 (righit/lower) is revised from “10b” to “11b”.
• NOTE 1 is added.
16.2.6 Output Impedance of Sensor under A/D Conversion
• 10th line: f(XIN) is revised to f(φAD).
Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit
• fAD is revised to φAD.
Figure 17.1 D/A Convertoer Block Diagram is revised.
Figure 17.2 DA0 and DA1 Registers: Setting Range is added.
Figure 17.3 D/A Converter Equivalent Circuit: NOTE 2 is added.
Figure 18.3 CRC Calculation is partly revised.
Figure 19.11 C0TECR, C1TECR Registers (2nd register): NOTE 1 is added.
Table 19.2 Examples of Bit-rate: NOTE 2 is added.
19.15.1 Reception: (5) is partly revised.
20. Programmable I/O Ports
• 8th line (Each pin functions ...) is partly revised.
• Last sentence (When using ...) is added.
• NOTE 1 is added.
20.1 PDi Register
• 4 th line: The sentence (During memory expansion ...) is added.
• NOTE 1 is added.
20.2 Pi Register
• 9 th line: The sentence (During memory expansion ...) is added.
• NOTE 1 is added.
20.3 PURj Register
• 5 th line: The sentence (However, the pull-up ...) is added.
• NOTE 1 is added.
Figure20.7 PDi Registers (upper): NOTE 2 is added.
Figure20.8 Pi Registers (upper): NOTE 2 is added.
Figure20.9 PUR0 Register (upper): NOTE 1 is added.
Figure20.9 PUR1 Register (middle): NOTES 1, 2 and 3 are added.
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