M16C6NK Datasheet, PDF (211/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
(1) Transmission
Transfer clock
TE bit in ^"1"
U2C1 register _"0"
TI bit in ^"1"
U2C1 register _"0"
TXD2
Parity error signal sent
back from receiving end
RXD2 pin level ⁽¹⁾
TXEPT bit in ^"1"
U2C0 register _"0"
IR bit in ^"1"
S2TIC register _"0"
TC
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P _SP
An "L" level returns due to the
occurrence of a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P
The level is detected by the
SP
interrupt routine.
The IR bit is set to "1" at the
falling edge of transfer clock
The level is
detected by the
interrupt routine.
The above timing diagram applies to the case where data is
transferred in the direct format.
STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)
Set to "0" by an interrupt request acknowledgement or a program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTE:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of the TXD2 output and the parity error signal sent back
from receiving end, is generated.
(2) Reception
TC
Transfer clock
RE bit in "1"
U2C1 register _"0"
Transmit waveform
from transmitting end
TXD2
RXD2 pin level ⁽¹⁾
RI bit in "1"
U2C0 register _"0"
IR bit in "1"
S2RIC register
"0"
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An "L" level is output from TXD2 due to
the occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
Read the U2RB register
Read the U2RB register
The above timing diagram applies to the case where data is
received in the direct format.
STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)
Set to "0" by an interrupt request acknowledgement or a program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTE:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the transmitting end and
parity error signal from receiving end, is generated.
Figure 15.32 Transmit and Receive Timing in SIM Mode
Rev.2.00 Nov 28, 2005 page 193 of 378
REJ09B0124-0200