M16C6NK Datasheet, PDF(102/404 Page) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

M16C6NK Datasheet, PDF (102/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

◁

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NK, M16C/6NM)

10. Interrupt

10.4 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective

interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the

corresponding interrupt vector. Figure 10.2 shows the interrupt vector.

MSB

LSB

Vector address (L)

Low-order address

Middle-order address

0000

High-order address

Vector address (H)

0000

0000

Figure 10.2 Interrupt Vector

10.4.1 Fixed Vector Tables

The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 10.1 lists the fixed

vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are

used by the ID code check function. For details, refer to 21.2 Functions to Prevent Flash Memory from

Rewriting.

Table 10.1 Fixed Vector Tables

Interrupt Source

Vector table Addresses

Address (L) to Address (H)

Reference

Undefined Instruction (UND instruction) FFFDCh to FFFDFh M16C/60, M16C/20, M16C/Tiny

Overflow (INTO instruction)

BRK Instruction (2)

FFFE0h to FFFE3h Series Software Manual

FFFE4h to FFFE7h

Address Match

Single Step (1)

FFFE8h to FFFEBh 10.10 Address Match Interrupt

FFFECh to FFFEFh

Oscillation Stop and Re-oscillation Detection, FFFF0h to FFFF3h 8. Clock Generating Circuit

Watchdog Timer

________

DBC (1)

_______

NMI

11. Watchdog Timer

FFFF4h to FFFF7h

_______

FFFF8h to FFFFBh 10.7 NMI Interrupt

Reset

FFFFCh to FFFFFh 5. Reset

NOTES:

1. Do not normally use this interrupt because it is provided exclusively for use by development tools.

2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the

vector in the relocatable vector table.

10.4.2 Relocatable Vector Tables

The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector

table area. Table 10.2 lists the relocatable vector tables. Setting an even address in the INTB register

results in the interrupt sequence being executed faster than in the case of odd addresses.

Rev.2.00 Nov 28, 2005 page 84 of 378

REJ09B0124-0200

▷