M16C6NK Datasheet, PDF (175/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
UARTi Special Mode Register 2 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR2 to U2SMR2
Address
01EEh, 01F2h, 01F6h
After Reset
X0000000b
Bit
Symbol
Bit Name
Function
RW
IICM2 I²C Mode Select Bit 2 See Table 15.12 I²C Mode Functions RW
Clock-Synchronous 0 : Disabled
CSC _Bit
1 : Enabled
RW
SWC
SCL Wait Output Bit
0 : Disabled
1 : Enabled
RW
ALS
SDA Output Stop Bit
0 : Disabled
1 : Enabled
RW
STAC
UARTi Initialization
Bit
0 : Disabled
1 : Enabled
RW
SWC2
SCL Wait Output
Bit 2
0: Transfer clock
1: "L" output
RW
SDHI
SDA Output Disable
Bit
0: Enabled
1: Disabled (high-impedance)
RW
- Nothing is assigned. When write, set to "0".
(b7) _{When read, its content is indeterminate.}
-
UARTi Special Mode Register 3 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3 to U2SMR3
Address
01EDh, 01F1h, 01F5h
After Reset
000X0X0Xb
Bit
Symbol
Bit Name
Function
RW
- Nothing is assigned When write, set to "0".
(b0) _{When read, its content is indeterminate.}
-
CKPH ^{Clock Phase Set Bit}
0 : Without clock delay
1 : With clock delay
RW
- ^{Nothing is assigned. When write, set to "0".}
(b2) When read, its content is indeterminate.
-
NODC
-
(b4)
Clock Output Select
Bit
0 : CLKi is CMOS output
1 : CLKi is N channel open-drain output ^RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
DL0
DL1
SDAi Digital Delay
Setup Bit (1) (2)
DL2
b7 b6 b5
0 0 0 : Without delay
RW
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source _RW
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source _RW
1 1 1 : 7 to 8 cycles of UiBRG count source
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I²C mode.
In other than I²C mode, set these bits to "000b" (no delay).
2. The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock,
the amount of delay increases by about 100 ns.
Figure 15.9 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
Rev.2.00 Nov 28, 2005 page 157 of 378
REJ09B0124-0200