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M16C6NK Datasheet, PDF (376/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES | |||
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
23. Usage Precaution
23.12.2 Special Modes
23.12.2.1 Special Mode 1 (I2C Mode)
When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to â0â
(start and stop conditions not output) and wait for more than half cycle of the transfer clock before setting
each condition generate bit (STAREQ, RSTAREQ and STPREQ bits) from â0â (clear) to â1â (start).
23.12.2.2 Special Mode 2
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If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
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output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.
23.12.2.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to â1â (transmission
complete) and U2ERE bit in the U2C1 register to â1â (error signal output) after reset. Therefore, when
using SIM mode, be sure to set the IR bit to â0â (no interrupt request) after setting these bits.
Rev.2.00 Nov 28, 2005 page 358 of 378
REJ09B0124-0200
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