M16C6NK Datasheet, PDF (260/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
19. CAN Module
19.12 Return from Bus Off Function
When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by
setting the RetBusOff bit in the CiCTLR register (i = 0, 1) to “1” (Force return from bus off). At this time, the
error state changes from bus off state to error active state. If the RetBusOff bit is set to “1”, the CiRECR and
CiTECR registers are initialized and the State_BusOff bit in the CiSTR register is set to “0” (CAN module is
not in error bus off state). However, registers of the CAN module such as CiCONR register and the content
of each slot are not initialized.
19.13 Time Stamp Counter and Time Stamp Function
When the CiTSR register ( i = 0, 1) is read, the value of the time stamp counter at the moment is read. The
period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the
CiCONR register. The time stamp counter functions as a free run counter.
The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference
clock. Use the TSPreScale bit in the CiCTLR register to select the divide-by-n value.
The time stamp counter is equipped with a register that captures the counter value when the protocol
controller regards it as a successful reception. The captured value is stored when a time stamp value is
stored in a reception slot.
19.14 Listen-Only Mode
When the RXOnly bit in the CiCTLR register ( i = 0, 1) is set to "1", the module enters listen-only mode.
In listen-only mode, no transmission, such as data frames, error frames, and ACK response, is performed
to bus.
When listen-only mode is selected, do not request the transmission.
Rev.2.00 Nov 28, 2005 page 242 of 378
REJ09B0124-0200