M16C6NK Datasheet, PDF (128/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
12. DMAC
12.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible.
Table 12.2 shows the number of DMA transfer cycles. Table 12.3 shows the coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k
Table 12.2 DMA Transfer Cycles
Transfer Unit
Bus Width
Single-chip Mode
Memory Expansion Mode
Microprocessor Mode ⁽¹⁾
Access Address
No. of Read No. of Write No. of Read No. of Write
Cycles
Cycles
Cycles
Cycles
16 bits
Even
1
1
1
1
8-bit Transfer
(BYTE = L)
Odd
1
1
1
1
(DMBIT =1)
8 bits
Even
-
-
1
1
(BYTE= H)
Odd
-
-
1
1
16 bits
Even
1
1
1
1
16-bit Transfer (BYTE =L)
Odd
2
2
2
2
(DMBIT = 0)
8 bits
Even
-
-
2
2
(BYTE = H)
Odd
-
-
2
2
-: This condition does not exist.
NOTE:
1. Not available memory expansion and microprocessor modes in T/V-ver..
Table 12.3 Coefficient j, k
Internal Area
External Area ⁽³⁾
Internal ROM, RAM
SFR
Separate Bus
Multiplexed Bus
No Wait With Wait 1 Wait ⁽¹⁾ 2 Waits ⁽¹⁾ No Wait
With Wait ⁽²⁾
With Wait ⁽²⁾
1 Wait 2 Waits 3 Waits 1 Wait 2 Waits 3 Waits
j
1
2
2
3
1
2
3
4
3
3
4
k1
2
2
3
2
2
3
4
3
3
4
NOTES:
1. Depends on the set value of the PM20 bit in the PM2 register.
2. Depends on the set value of the CSE register.
3. Not available external area in T/V-ver..
Rev.2.00 Nov 28, 2005 page 110 of 378
REJ09B0124-0200