M16C6NK Datasheet, PDF (329/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
22. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
Read timing
VCC = 5V
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
td(BCLK-CS)
tcyc
25ns.max
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
Address
td(BCLK-AD)
25ns.max
th(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
tdZ(RD-AD)
8ns.max
tac3(RD-DB)
(1.5 ✕ tcyc-45)ns.max
td(AD-RD)
0ns.min
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-RD)
25ns.max
th(RD-CS)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-CS)
4ns.min
Data input
tSU(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Address
th(BCLK-AD)
4ns.min
th(RD-AD)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-RD)
0ns.min
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
td(BCLK-CS)
25ns.max
Address
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
td(BCLK-AD)
25ns.max
tcyc
td(BCLK-DB)
40ns.max
Data output
td(DB-WR)
(1.5 ✕ tcyc-40)ns.min
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
td(BCLK-WR)
25ns.max
tcyc = ¹
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 22.10 Timing Diagram (7)
th(WR-CS)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-CS)
4ns.min
th(BCLK-DB)
4ns.min
Address
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-WR)
0ns.min
Rev.2.00 Nov 28, 2005 page 311 of 378
REJ09B0124-0200