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M16C6NK Datasheet, PDF (129/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES | |||
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
12. DMAC
12.3 DMA Enable
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to â1â (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register
is â1â (forward) or the DARi register value when the DAD bit in the DMiCON register is â1â (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to â1â again while it remains set, the DMAC performs the above operation.
However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps
below.
Step 1: Write â1â to the DMAE bit and DMAS bit in the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
12.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS
and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 12.4 shows the timing at
which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to â1â (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to â1â (enabled) when this occurred, the DMAS bit is set
to â0â (DMA not requested) immediately before a data transfer starts. This bit cannot be set to â1â in a
program (it can only be set to â0â).
The DMAS bit may be set to â1â when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to â0â after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is â1â, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is â0â when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 12.4 Timing at Which DMAS bit Changes State
DMA Factor
DMAS Bit in DMiCON Register
Timing at which the bit is set to â1â Timing at which the bit is set to â0â
Software Trigger
When the DSR bit in the DMiSL register ⢠Immediately before a data transfer starts
is set to â1â
⢠When set by writing â0â in a program
Peripheral Function When the interrupt control register for
the peripheral function that is selected
by the DSEL3 to DSEL0 and DMS bits
in the DMiSL register has its IR bit set to â1â.
i = 0, 1
Rev.2.00 Nov 28, 2005 page 111 of 378
REJ09B0124-0200
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