M16C6NK Datasheet, PDF (117/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
10. Interrupt
10.10 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER0 and AIER1 bits in the AIER register and the AIER20 and AIER21 bits in the AIER2
register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag
and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending
on the instruction being executed (refer to 10.5.7 Saving Registers). (The value of the PC that is saved to
the stack area is not the correct return address.) Therefore, follow one of the methods described below to
return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 10.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted. Table 10.7 shows the relationship between address match interrupt sources and associated
registers.
Note that when using the external bus in 8-bit width, no address match interrupts can be used for external
areas. (External bus is available Nomal-ver. only.)
Figure 10.16 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 10.6 Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted
Instruction at Address Indicated by RMADi Register
Value of PC that is Saved to Stack Area
• 16-bit operation code
Address indicated by RMADi
• Instruction shown below among 8-bit operation code instructions register + 2
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S
STNZ.B:S
CMP.B:S
JMPS
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
MOV.B:S
STZX.B:S
PUSHM
JSRS
#IMM8,dest STZ.B:S #IMM8,dest
#IMM81,#IMM82,dest
src
POPM dest
#IMM8
MOV.B:S #IMM,dest (However, dest = A0 or A1)
Instructions other than the above
Address indicated by RMADi
register + 1
Value of PC that is saved to stack area: Refer to 10.5.7 Saving Registers.
Table 10.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Sources Address Match Interrupt Enable Bit Address Match Interrupt Register
Address Match Interrupt 0 AIER0
RMAD0
Address Match Interrupt 1 AIER1
RMAD1
Address Match Interrupt 2 AIER20
RMAD2
Address Match Interrupt 3 AIER21
RMAD3
Rev.2.00 Nov 28, 2005 page 99 of 378
REJ09B0124-0200