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M16C6NK Datasheet, PDF (371/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES | |||
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
23. Usage Precaution
23.10.1.4 Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to â1â (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register are modified while the TAiS bit remains â0â (count stops) regardless whether after reset
or not.
The IR bit is set to â1â when setting a timer operation mode with any of the following procedures:
⢠Select the pulse width modulation mode after reset.
⢠Change an operation mode from timer mode to pulse width modulation mode.
⢠Change an operation mode from event counter mode to pulse width modulation mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to â0â by program after the above listed changes
have been made.
When setting TAiS bit to â0â (count stop) during PWM pulse output, the following action occurs:
⢠Stop counting.
⢠When TAiOUT pin is output âHâ, output level is set to âLâ and the IR bit is set to â1â.
⢠When TAiOUT pin is output âLâ, both output level and the IR bit remain unchanged.
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If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
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phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
Rev.2.00 Nov 28, 2005 page 353 of 378
REJ09B0124-0200
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