M16C6NK Datasheet, PDF (109/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
10. Interrupt
10.5.7 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
10.7 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
MSB
LSB
Address
m-4
m-3
m-2
m-1
m
Content of previous stack
m + 1 Content of previous stack
[SP]
SP value before
interrupt request
is accepted.
Stack
MSB
LSB
Address
m-4
PCL
m-3
PCM
m-2
FLGL
m-1
FLGH
PCH
m
Content of previous stack
m + 1 Content of previous stack
[SP]
New SP value
Stack status before interrupt request is acknowledged
PCL : 8 low-order bit of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
Stack status after interrupt request is acknowledged
Figure 10.7 Stack Status Before and After Acceptance of Interrupt Request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP ⁽¹⁾,
at the time of acceptance of an interrupt request, is even or odd. If the SP (Note) is even, the FLG register
and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 10.8
shows the operation of the saving registers.
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1)SP contains even number
Address
Stack
[SP] - 5 (Odd)
[SP] - 4 (Even)
[SP] - 3 (Odd)
[SP] - 2 (Even)
[SP] - 1 (Odd)
[SP] (Even)
PCL
PCM
FLGL
FLGH
PCH
(2)SP contains odd number
Sequence in which order
registers are saved
Address
Stack
[SP] - 5 (Even)
(2) Saved simultaneously, ^{[SP] - 4 (Odd)}
all 16 bits
[SP] - 3 (Even)
(1) Saved simultaneously, ^{[SP] - 2 (Odd)}
all 16 bits
[SP] - 1 (Even)
Finished saving registers
in two operations.
[SP] (Odd)
PCL
PCM
FLGL
FLGH
PCH
Sequence in which order
registers are saved
(3)
(4) _{Saved,8 bits}
(1) ^{at a time}
(2)
Finished saving registers
in four operations.
PCL : 8 low-order bit of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
NOTE:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 10.8 Operation of Saving Registers
Rev.2.00 Nov 28, 2005 page 91 of 378
REJ09B0124-0200