M16C6NK Datasheet, PDF (113/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
10. Interrupt
Interrupt Request Cause Select Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR0
Address
01DEh
After Reset
00h
Bit Symbol
Bit Name
IFSR00
Interrupt Request Cause
Select Bit ⁽¹⁾
Function
RW
0 : CAN1 successful transission
1 : SI/O3
RW
IFSR01
IFSR02
IFSR03
Interrupt Request Cause
Select Bit ⁽²⁾
Interrupt Request Cause
Select Bit ⁽³⁾
Interrupt Request Cause
Select Bit ⁽⁴⁾
0 : A/D conversion
1 : Key input
RW
0 : CAN0/1 wake-up or error
1 : CAN0 wake-up/error or
RW
CAN1 wake-up/error
0 : CAN1 successful reception
1 : SI/O4
RW
IFSR04
Interrupt Request Cause
Select Bit ⁽⁵⁾
0 : Timer B5
1 : SI/O5
RW
IFSR05
IFSR06
Interrupt Request Cause
Select Bit ⁽⁶⁾
Interrupt Request Cause
Select Bit ⁽⁷⁾
0 : Timer B0
1 : SI/O6
RW
0 : Timer B3
1 : UART0 bus collision detection
RW
IFSR07
Interrupt Request Cause
Select Bit ⁽⁸⁾
0 : Timer B4
1 : UART1 bus collision detection
RW
NOTES:
1.When the IFSR16 bit in the IFSR1 register = 0, CAN1 successful transmission and SI/O3 share the
vector and interrupt control register. When using the CAN1 successful transmission interrupt, set the
IFSR00 bit to "0" (CAN1 successful transmission). When using SI/O3 interrupt, set the IFSR00 bit to
"1" (SI/O3).
2.When the PCLK6 bit in the PCLKR register = 0, A/D conversion and key input share the vector and
interrupt control register. When using the A/D conversion interrupt, set the IFSR01 bit to "0" (A/D
conversion). When using the key input interrupt, set the IFSR01 bit to "1" (key input).
3.If this bit is set to "0", the software interrupt number 1 is selected CAN0/1 wake-up and the interrupt
number 13 is selected CAN0/1 error. If this bit is set to "1", the interrupt number 1 is selected CAN0
wake-up/error and the interrupt number 13 is selected CAN1 wake-up/error.
4.When the IFSR17 bit in the IFSR1 register = 0, CAN1 successful reception and SI/O4 share the vector
and interrupt control register. When using the CAN1 successful reception interrupt, set the IFSR03 bit
to "0" (CAN1 successful reception). When using SI/O4 interrupt, set the IFSR03 bit to "1" (SI/O4).
5.Timer B5 and SI/O5 share the vector and interrupt control register. When using the timer B5 interrupt,
set the IFSR04 bit to "0" (Timer B5). When using SI/O5 interrupt, set the IFSR04 bit to "1" (SI/O5).
The SI/O5 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to "0"
(Timer B5).
6.Timer B0 and SI/O6 share the vector and interrupt control register. When using the timer B0 interrupt,
set the IFSR05 bit to "0" (Timer B0). When using SI/O6 interrupt, set the IFSR05 bit to "1" (SI/O6).
The SI/O6 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to "0"
(Timer B0).
7.Timer B3 and UART0 bus collision detection share the vector and interrupt control register.
When using the timer B3 interrupt, set the IFSR06 bit to "0" (Tmer B3).
When using UART0 bus collision detection, set the IFSR06 bit to "1" (UART0 bus collision detection).
8.Timer B4 and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4 interrupt, set the IFSR07 bit to "0" (Timer B4).
When using UART1 bus collision detection, set the IFSR07 bit to "1" (UART1 bus collision detection).
Figure 10.11 IFSR0 Register
Rev.2.00 Nov 28, 2005 page 95 of 378
REJ09B0124-0200