M16C6NK Datasheet, PDF (133/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
13. Timers
13.1 Timer A
Figure 13.3 shows a block diagram of the timer A. Figures 13.4 to 13.6 show the timer A-related registers.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode:
The timer counts an internal count source.
• Event counter mode:
The timer counts pulses from an external device or overflows and
underflows of other timers.
• One-shot timer mode:
The timer outputs a pulse only once before it reaches the minimum count “0000h.”
• Pulse width modulation mode: The timer outputs pulses in a given width successively.
Select Clock source
f1 or f2
f8
f32
fC32
00 ^{TCK1 to TCK0}
01
10
11
TAiIN
Polarity
selection
Select clock
Timer
One shot
Pulse width
modulation
:
:
:
TMOD1
TMOD1
TMOD1
to
to
to
TMOD0
TMOD0
TMOD0
=
=
=
00,
10
11
MR2
=
0
TMOD1
MR2
to
TMOD0,
Timer (gate function) : TMOD1 to TMOD0 = 00, MR2 = 1
Event counter
: TMOD1 to TMOD0 = 01
High-order Bits of Data Bus
Low-order Bits of Data Bus
Low-order
8 bits
Reload Register
High-order
8 bits
00
01
TB2 overflow (1) ₁₀
TAj overflow (1)
TAk overflow (1)
11
TAiTGH to TAiTGL
TAiS
To external trigger circuit
00
10
11
Decrement
01
Counter
Increment/Decrement
Always counts down except
in event counter mode
TAiUD ⁰
1
TMOD1 to TMOD0
Pulse output
MR2
TAiOUT
Toggle Flip-Flop
TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1: Bits in TAiMR register
TAiTGH to TAiTGL: Bits in ONSF register If i = 0, bits in TRGSR register if i = 1 to 4
TAiS: Bit in TABSR register
TAiUD: Bit in UDF register
i = 0 to 4
j = i - 1except j = 4 when i = 0
k = i + 1 except k = 0 when i = 4
NOTE:
1. Overflow or underflow
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
0387h - 0386h
0389h - 0388h
038Bh- 038Ah
038Dh- 038Ch
038Fh- 038Eh
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
Figure 13.3 Timer A Block Diagram
Rev.2.00 Nov 28, 2005 page 115 of 378
REJ09B0124-0200