M16C6NK Datasheet, PDF (299/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
21. Flash Memory Version
Full status check
FMR06 =1
and
FMR07=1?
YES
Command
sequence error
(1) Execute the clear status register command and set the SR4 and SR5
bits to "0" (completed as expected).
(2) Rewrite command and execute again.
NO
FMR07=0?
NO
Erase error
YES
(1) Execute the clear status register command and set the SR5 bit to "0".
(2) Execute the lock bit read status command. Set the FMR02 bit in the
FMR0 register to "1" (lock bit disabled) if the lock bit in the block where
the error occurred is set to "0" (locked).
(3) Execute the block erase or erase all unlocked block command again.
(4) Execute (1), (2) and (3) at least 3 times until an erase error is not
generated.
NOTE: If similar error occurs, that block cannot be used.
If the lock bit is set to "1" (unlocked) in (2) above, that block cannot
be used.
FMR06=0?
YES
NO
Program error
Full status check completed
[When a program operation is executed]
(1) Execute the clear status register command and set the SR4 bit to "0"
(completed as expected).
(2) Execute the read lock bit status command and set the FMR02 bit to "1"
if the lock bit in the block where the error occurred is set to "0".
(3) Execute the program command again.
NOTE: When a similar error occurs, that block cannot be used.
If the lock bit is set to "1" in (2) above, that block cannot be used.
[When a lock bit program operation is executed]
(1) Execute the clear status register command and set the SR4 bit to "0".
(2) Set the FMR02 bit to "1".
(3) Execute the block erase command to erase the block where the error
occurred.
(4) Execute the lock bit program command again.
NOTE: If similar error occurs, that block cannot be used.
FMR06, FMR07: Bits in FMR0 register
NOTE:
1. When either FMR06 or FMR07 bit is set to "1" (terminated by error), the program, block erase, erase all unlocked block, lock bit program
and read lock bit status commands cannot be accepted.
Execute the clear status register command before each command.
Figure 21.12 Full Status Check and Handling Procedure for Each Error
Rev.2.00 Nov 28, 2005 page 281 of 378
REJ09B0124-0200