M16C6NK Datasheet, PDF (208/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
(1) ABSCS Bit in UiSMR Register (bus collision detect sampling clock select)
If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RXDi
Input to TAjIN
Timer Aj
If ABSCS bit = 1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) ACSE Bit in UiSMR Register (auto clear of transmit enable bit)
Transfer clock
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RXDi
IR bit in
UiBCNIC register
TE bit in
UiC1 register
If the ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is set to "0"
(transmission disabled) when
the IR bit in the UiBCNIC register = 1
(unmatching detected).
(3) SSS Bit in UiSMR Register (transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge ⁽¹⁾ of RXDi
CLKi
TXDi
(NOTE 2)
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
RXDi
NOTES:
1.The falling edge of RXDi when IOPOL bit = 0; the rising edge of RXDi when IOPOL bit = 1.
2. The transmit condition must be met before the falling edge ⁽¹⁾ of RXDi.
i = 0 to 2
This diagram applies to the case where IOPOL bit =1 (reversed)
Figure 15.31 Bus Collision Detect Function-Related Bits
Rev.2.00 Nov 28, 2005 page 190 of 378
REJ09B0124-0200