M16C6NK Datasheet, PDF (152/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
13. Timers
13.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Table 13.7 lists specifications in event counter mode. Figure 13.19 shows TBiMR register in
event counter mode.
Table 13.7 Specifications in Event Counter Mode
Item
Specification
Count Source
• External signals input to TBiIN pin (effective edge can be selected in program)
• Timer Bj overflow or underflow
Count Operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide Ratio
Count Start Condition
1/(n+1) n: set value of the TBi register 0000h to FFFFh
Set TBiS bit ⁽¹⁾ to “1” (start counting)
Count Stop Condition Set TBiS bit to “0” (stop counting)
Interrupt Request Generation Timing Timer underflow
TBiIN Pin Function
Count source input
Read from Timer
Count value can be read by reading the TBi register
Write to Timer
• When not counting and until the 1st count source is input after counting start
Value written to the TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i= 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039Bh to 039Dh
01DBh to 01DDh
After Reset
00XX0000b
00XX0000b
Bit Symbol
Bit Name
Function
RW
TMOD0
b1 b0
RW
Operation Mode Select Bit _{0 1 : Event counter mode}
TMOD1
RW
MR0
MR1
MR2
Count Polarity Select
Bit ⁽¹⁾
b3 b2
0 0 : Counts falling edge of external signal _RW
0 1 : Counts rising edge of external signal
1 0 : Counts falling and rising edges of
external signal
RW
1 1 : Do not set a value
TB0MR, TB3MR registers
Set to "0" in event counter mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
-
When read, its content is indeterminate.
When write in event counter mode, set to "0".
MR3
When read in event counter mode, its content is indeterminate.
RO
TCK0
Has no effect in event counter mode.
Can be set to "0" or "1".
RW
0 : Input from TBiIN pin ⁽²⁾
TCK1
Event Clock Select Bit
1 : TBj overflow or underflow
(j = i — 1, except j = 2 if i = 0,
RW
j = 5 if i = 3)
NOTES:
1. Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits can
be set to "0" or "1".
2. The port direction bit for the TBiIN pin must be set to "0" (input mode).
Figure 13.19 TB0MR to TB5MR Registers in Event Counter Mode
Rev.2.00 Nov 28, 2005 page 134 of 378
REJ09B0124-0200