M16C6NK Datasheet, PDF (281/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
21. Flash Memory Version
ROM Code Protect Control Address ⁽⁵⁾
b7 b6 b5 b4 b3 b2 b1 b0
111111
Symbol
ROMCP
Address
0FFFFFh
Value when Shipped
FFh ⁽¹⁾
Bit Symbol
Bit Name
Function
RW
-
(b5-b0)
Reserved Bit
Set to "1"
RW
b7 b6
00:
RW
ROMCP1
ROM Code Protect Level 1 _{0 1 : Protect enabled}
Set Bit ^{(1) (2) (3) (4)}
10:
1 1 : Protect disabled
RW
NOTES:
1. The ROMCP address is set to "FFh" when a block, including the ROMCP address, is erased.
2. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against
reading or rewriting in parallel I/O mode.
3. Set the bit 5 to bit 0 to "111111b" when the ROMCP1 bit is set to a value other than "11b".
If the bit 5 to bit 0 are set to values other than "111111b", the ROM code protection may not become active
by setting the ROMCP1 bit to a value other than "11b".
4. To make the ROM code protection inactive, erase a block including the ROMCP address in CPU rewrite
mode, standard serial I/O mode or CAN I/O mode.
5. When a value of the ROMCPaddress is "00h" or "FFh", the ROM code protect function is disabled.
Figure 21.2 ROMCP Register
Address
0FFFDFh to 0FFFDCh ID1 Undefined instruction vector
0FFFE3h to 0FFFE0h ID2 Overflow vector
0FFFE7h to 0FFFE4h
BRK instruction vector
0FFFEBh to 0FFFE8h ID3 Address match vector
0FFFEFh to 0FFFECh ID4 Single step vector
0FFFF3h to 0FFFF0h ID5 Oscillation stop and re-oscillation detection/Watchdog timer vector
0FFFF7h to 0FFFF4h ID6 DBC vector
0FFFFBh to 0FFFF8h ID7 NMI vector
0FFFFFh to 0FFFFCh ROMCP ^{Reset vector}
Figure 21.3 Address for ID Code Stored
4 bytes
Rev.2.00 Nov 28, 2005 page 263 of 378
REJ09B0124-0200