M16C6NK Datasheet, PDF (188/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
(1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked.
TC
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
Transfer clock
TE bit in
"1"
UiC1 register
"0"
TI bit in
"1"
UiC1 register
"0"
"H"
CTSi
"L"
TXDi
TXEPT bit in
"1"
UiC0 register
"0"
IR bit in
"1"
SiTIC register
"0"
Write data to the UiTB register
Transferred from UiTB register to UARTi transmit register
Start
bit
Parity Stop
bi t bi t
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped pulsing
because the TE bit
=0
ST D0 D1
Set to "0" by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
as follows:
PRYE bit in UiMR register = 1 (parity enabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), and CRS bit = 0 (CTS selected)
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
UilRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
i = 0 to 2
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Transmit Timing when Transfer Data is 9-bit Long (parity disabled, two stop bits)
TC
Transfer clock
TE bit in
"1"
UiC1 register
"0"
TI bit in
"1"
UiC1 register
"0"
TXDi
TXEPT bit in
"1"
UiC0 register
"0"
IR bit in
"1"
SiTIC register
"0"
Write data to the UiTB register
Start
bit
Stop Stop
bi t bi t
Transferred from UiTB register to UARTi
transmit register
ST D 0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
Set to "0" by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set
as follows:
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 1 (2 stop bits)
CRD bit in UiC0 register = 1 (CTS/RTS disabled)
UilRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of UiBRG count source (external clock)
n : value set to UiBRG
i = 0 to 2
Figure 15.17 Transmit Operation
Rev.2.00 Nov 28, 2005 page 170 of 378
REJ09B0124-0200