M16C6NK Datasheet, PDF (247/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
19. CAN Module
CANi Control Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CTLR
C1CTLR
Address
0210h
0230h
After Reset
X0000001b
X0000001b
Bit Symbol
Bit Name
Function
RW
CAN Module
0: Operation mode
Reset
Reset Bit ⁽¹⁾
1: Reset/initialization mode
RW
LoopBack
Loop Back Mode
Select Bit ⁽²⁾
0: Loop back mode disabled
1: Loop back mode enabled
RW
Message Order
MsgOrder _{Select Bit (2)}
0: Word access
1: Byte access
RW
Basic CAN Mode 0: Basic CAN mode disabled
BasicCAN _{Select Bit (2)}
1: Basic CAN mode enabled
RW
BusErrEn
Bus Error Interrupt
Enable Bit ⁽²⁾
0: Bus error interrupt disabled
1: Bus error interrupt enabled
RW
Sleep
Sleep Mode
Select Bit ^{(2) (3)}
0: Sleep mode disabled
1: Sleep mode enabled; clock supply stopped ^RW
PortEn
CAN Port Enable 0: I/O port function
Bit ^{(2) (3)}
1: CTX/CRX function
RW
-
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
-
NOTES:
1. When the Reset bit is set to "1" (CAN reset/initialization mode), check that the State_Reset bit in the CiSTR register is set to
"1" (Reset mode).
2. Change this bit only in the CAN reset/initialization mode.
3. When using CAN0/1 wake-up interrupt, set these bits to "1".
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CTLR
C1CTLR
Address
0211h
0231h
After Reset
XX0X0000b
XX0X0000b
Bit Symbol
Bit Name
Function
RW
b1 b0
0 0: Period of 1 bit time
TSPreScale
Time Stamp
Prescaler ⁽³⁾
0 1: Period of 1/2 bit time
1 0: Period of 1/4 bit time
RW
1 1: Period of 1/8 bit time
TSReset
Time Stamp Counter 0: Nothing is occurred.
Reset Bit ⁽¹⁾
1: Force reset of the time stamp counter
RW
RetBusOff
Return From Bus Off 0: Nothing is occurred.
Command Bit ⁽²⁾ 1: Force return from bus off
RW
-
Nothing is assigned. When write, set to "0".
-
(b4)
When read, its content is indeterminate.
RXOnly
Listen-Only Mode 0: Listen-only mode disabled
Select Bit ⁽³⁾
1: Listen-only mode enabled (4)
RW
-
Nothing is assigned. When write, set to "0".
-
(b7-b6) _{When read, their contents are indeterminate.}
NOTES:
1. When the TSReset bit = 1, the CiTSR register is set to "0000h". After this, the bit is automatically set to "0".
2. When the RetBusOff bit = 1, the CiRECR and CiTECR registers are set to "00h". After this, this bit is automatically set to "0".
3. Change this bit only in the CAN reset/initialization mode.
4. When the listen-only mode is selected, do not request the transmission.
Figure 19.7 C0CTLR and C1CTLR Registers
Rev.2.00 Nov 28, 2005 page 229 of 378
REJ09B0124-0200