M16C6NK Datasheet, PDF (124/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
12. DMAC
DMA1 Request Cause Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BAh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
DSEL0
RW
DSEL1
DSEL2
DMA Request Cause
Select Bit
See NOTE 1
RW
RW
DSEL3
RW
-
Nothing is assigned. When write, set to "0".
(b5-b4) _{When read, their contents are "0".}
-
DMS
DMA Request Cause 0 : Basic cause of request
Expansion Select Bit 1 : Extended cause of request
RW
DSR
Software DMA
Request Bit
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0 RW
bits are "0001b" (software trigger).
The value of this bit when read is "0".
NOTE:
1. The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
DSEL3 to DSEL0 Bits DMS = 0 (basic cause of request)
0000b
Falling edge of INT1 pin
0001b
Software trigger
0010b
Timer A0
0011b
Timer A1
0100b
Timer A2
0101b
Timer A3
0110b
Timer A4
0111b
Timer B0
1000b
Timer B1
1001b
Timer B2
1010b
UART0 transmit
1011b
UART0 receive/ACK0
1100b
UART2 transmit
1101b
UART2 receive/ACK2
1110b
A/D conversion
1111b
UART1 transmit/ACK1
DMS = 1 (extended cause of request)
—
—
—
—
—
SI/O3
SI/O4
Two edges of INT1 pin
—
—
—
—
—
—
—
—
DMAi Control Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Address
002Ch
003Ch
After Reset
00000X00b
00000X00b
Bit Symbol
Bit Name
Function
RW
DMBIT
Transfer Unit Bit
Select Bit
0 : 16 bits
1 : 8 bits
RW
DMASL
Repeat Transfer Mode
Select Bit
0 : Single transfer
1 : Repeat transfer
RW
DMAS DMA Request Bit
0 : DMA not requested
1 : DMA requested
RW ⁽¹⁾
DMAE DMA Enable Bit
0 : Disabled
1 : Enabled
RW
DSD
Source Address Direction 0 : Fixed
Select Bit ⁽²⁾
1 : Forward
RW
DAD
Destination Address
Direction Select Bit ⁽²⁾
0 : Fixed
1 : Forward
RW
-
(b7-b6)
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTES:
1. The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 12.3 DM1SL Register, DM0CON and DM1CON Registers
Rev.2.00 Nov 28, 2005 page 106 of 378
REJ09B0124-0200