M16C6NK Datasheet, PDF (194/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
SDAi
Delay
circuit
STSPSEL=1
STSPSEL=0
ACKC=1 ACKC=0
ACKD bit
Noise
Filter
SDHI _ALS
D _{Q Arbitration}
T
Start condition
detection
Stop condition
detection
Start and stop condition generation block
SDA(STSP)
SCL(STSP)
Transmission
register
UARTi
IICM2=1
IICM=1 and
IICM2=0
Reception register
UARTi
S
Q
Bus
R _busy
IICM2=1
IICM=1 and
IICM2=0
NACK
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
DMA0
(UART0, UART2)
UARTi receive,
ACK interrupt request,
DMA1 request
SCLi
Noise
Filter
Falling edge
detection
IICM=0
R
I/O port _Q
STSPSEL=0
Port register ⁽¹⁾
Internal clock
DQ
T
DQ
T
9th bit
ACK
IICM=1UARTi
STSPSEL=1
SWC2
External
clock
CLK
control
UARTi
R
9th bit falling edge
S
SWC
Start/stop condition
detection
interrupt request
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
i = 0 to 2
IICM: Bit in UiSMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in UiSMR2 register
STSPSEL, ACKD, ACKC: Bits in UiSMR4 register
NOTE:
1. If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 15.23 I²C Mode Block Diagram
Rev.2.00 Nov 28, 2005 page 176 of 378
REJ09B0124-0200