M16C6NK Datasheet, PDF (263/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
19.15.2 Transmission
Figure 19.21 shows the timing of the transmit sequence.
19. CAN Module
SOF
CTX
ACK
EOF
IFS SOF
TrmReq bit
(1)
TrmActive bit
(1)
(2)
(4)
(3)
SentData bit
(3)
CANi Successful
(3)
Transmission Interrupt
TrmState bit
(1)
(2)
TrmSucc bit
MBOX bit
Transmission slot No.
i = 0, 1
j = 0 to 15
Figure 19.21 Timing of Transmit Sequence
(1) If the TrmReq bit in the CiMCTLj register (i = 0, 1, j = 0 to 15) is set to “1” (Transmission slot) in the bus
idle state, the TrmActive bit in the CiMCTLj register and the TrmState bit in the CiSTR register are set
to “1” (Transmitting/Transmitter), and CAN module starts the transmission.
(2) If the arbitration is lost after the CAN module starts the transmission, the TrmActive and TrmState bits
are set to “0”.
(3) If the transmission has been successful without lost in arbitration, the SentData bit in the CiMCTLj
register is set to “1” (Transmission is successfully completed) and TrmActive bit is set to “0” (Waiting
for bus idle or completion of arbitration). And when the interrupt enable bits in the CiICR register = 1
(Interrupt enabled), CANi successful transmission interrupt request is generated and the MBOX (the
slot number which transmitted the message) and TrmSucc bit in the CiSTR register are changed.
(4) When starting the next transmission, set the SentData and TrmReq bits to “0”. And set the TrmReq bit
to “1” after checking that the SentData and TrmReq bits are set to “0”.
Rev.2.00 Nov 28, 2005 page 245 of 378
REJ09B0124-0200