M16C6NK Datasheet, PDF (250/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
19. CAN Module
CANi Configuration Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
C1CONR
Address
021Ah
023Ah
After Reset
Indeterminate
Indeterminate
Bit Symbol
Bit Name
Function
RW
b3 b2 b1 b0
0 0 0 0 : Divide-by-1 of fCAN
BRP
Prescaler Division
Ratio Select Bits
0 0 0 1 : Divide-by-2 of fCAN
0 0 1 0 : Divide-by-3 of fCAN
RW
1 1 1 0 : Divide-by-15 of fCAN
1 1 1 1 : Divide-by-16 of fCAN ⁽¹⁾
Sampling Control 0 : One time sampling
SAM _Bit
1 : Three times sampling
RW
b7 b6 b5
0 0 0 : 1Tq
Propagation Time 0 0 1 : 2Tq
PTS Segment Control ^{0 1 0 : 2Tq}
RW
Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
NOTE:
1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bit (i = 0 to 2, 4 to 6) in the CCLKR register.
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
C1CONR
Address
021Bh
023Bh
After Reset
Indeterminate
Indeterminate
Bit Symbol
Bit Name
Function
RW
b2 b1b0
0 0 0 : Do not set a value
Phase Buffer
0 0 1 : 2Tq
PBS1 Segment 1
0 1 0 : 3Tq
RW
Control Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
b5 b4 b3
0 0 0 : Do not set a value
Phase Buffer
0 0 1 : 2Tq
PBS2 Segment 2
0 1 0 : 3Tq
RW
Control Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
b7 b6
Resynchronization 0 0 : 1Tq
SJW Jump Width
0 1 : 2Tq
RW
Control Bits
1 0 : 3Tq
1 1 : 4Tq
Figure 19.10 C0CONR and C1CONR Registers
Rev.2.00 Nov 28, 2005 page 232 of 378
REJ09B0124-0200