M16C6NK Datasheet, PDF (174/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B0h
After Reset
X0000000b
Bit
Symbol
Bit Name
Function
RW
U0IRS
UART0 Transmit Interrupt
Cause Select Bit
0 : Transmit buffer empty (Tl bit = 1)
1 : Transmission completed (TXEPT bit = 1)
RW
UART1 Transmit Interrupt 0 : Transmit buffer empty (Tl bit = 1)
U1IRS _{Cause Select Bit}
1 : Transmission completed (TXEPT bit = 1) ^RW
U0RRM
UART0 Continuous
Receive Mode Enable Bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U1RRM
UART1 Continuous
Receive Mode Enable Bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
CLKMD0
UART1 CLK/CLKS
Select Bit 0
Effective when the CLKMD1 bit = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
RW
CLKMD1
UART1 CLK/CLKS
Select Bit 1 ⁽¹⁾
0 : CLK output is only CLK1
1 : Transfer clock output from multiple RW
pins function selected
RCSP
Separate UART0
CTS/RTS Bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated
RW
(CTS0 supplied from the P6_4 pin)
- _{Nothing is assigned. When write, set to "0".}
(b7) _{When read, its content is indeterminate.}
-
NOTE:
1. When using multiple transfer clock output pins, make sure the following conditions are met:
The CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0SMR to U2SMR
Address
01EFh, 01F3h, 01F7h
After Reset
X0000000b
Bit
Symbol
Bit Name
Function
RW
IICM
I²C Mode Select Bit
0 : Other than I²C mode
1 : I²C mode
RW
Arbitration Lost Detecting 0 : Update per bit
ABC _{Flag Control Bit}
1 : Update per byte
RW
BBS Bus Busy Flag
0 : STOP condition detected
1 : START condition detected (busy)
RW ⁽¹⁾
-
(b3)
Reserved Bit
Set to "0"
RW
ABSCS
Bus Collision Detect
Sampling Clock Select Bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj ⁽²⁾
RW
Auto Clear Function 0 : No auto clear function
ACSE Select Bit of Transmit 1 : Auto clear at occurrence of bus
RW
Enable Bit
collision
SSS
Transmit Start Condition 0 : Not synchronized to RXDi
Select Bit
1 : Synchronized to RXDi ⁽³⁾
RW
- Nothing is assigned. When write, set to "0".
(b7) _{When read, its content is indeterminate.}
-
NOTES:
1. The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
2. Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer
A0 in UART2.
3. When a transfer begins, the SSS bit is set to "0" (not synchronized to RXDi).
Figure 15.8 UCON Register and U0SMR to U2SMR Registers
Rev.2.00 Nov 28, 2005 page 156 of 378
REJ09B0124-0200