M16C6NK Datasheet, PDF (196/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
Table 15.12 I²C Mode Functions
Function
Clock
I²C Mode (SMD2 to SMD0 = 010b, IICM = 1)
Synchronous
Serial I/O Mode
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/receive interrupt)
(SMD2 to SMD0 = _{CKPH = 0}
001b, IICM = 0) _{(No clock delay)}
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Factor of Interrupt -
Start condition detection or stop condition detection
Number 6, 7 and
(See Table 15.13 STSPSEL Bit Functions)
10 ^{(1) (5) (7)}
Factor of Interrupt UARTi transmission No acknowledgment detection
UARTi transmission UARTi transmission
Number 15, 17 and Transmission started (NACK)
Rising edge of Falling edge of
19 ^{(1) (6)}
or completed
Rising edge of SCLi 9th bit
SCLi 9th bit
SCLi next to the
(selected by UiIRS)
9th bit
Factor of Interrupt UARTi reception Acknowledgment detection (ACK) UARTi reception
Number 16, 18 and When 8th bit received Rising edge of SCLi 9th bit
Falling edge of SCLi 9th bit
20 ^{(1) (6)}
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for Transferring CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit
Falling edge of Falling and rising
Data from UART CKPOL = 1 (falling edge)
SCLi 9th bit
edges of SCLi 9th
Reception Shift Register
bit
to UiRB Register
UARTi Transmission _{Not delayed}
Output Delay
Delayed
Functions of P6_3, TXDi output
SDAi input/output
P6_7 and P7_0 Pins
Functions of P6_2, RXDi input
SCLi input/output
P6_6 and P7_1 Pins
Functions of P6_1, CLKi input or - (Cannot be used in I²C mode)
P6_5 and P7_2 Pins output selected
Noise Filter Width 15 ns
200 ns
Read RXDi and Possible when the Always possible no matter how the corresponding port direction bit is set
SCLi Pins Levels corresponding port
direction bit = 0
Initial Value of TXDi CKPOL = 0 (H) The value set in the port register before setting I²C mode ⁽²⁾
and SDAi Outputs CKPOL = 1 (L)
Initial and End
-
H
L
H
L
Value of SCLi
DMA1 Factor ⁽⁶⁾
UARTi reception Acknowledgment detection (ACK) UARTi reception
Falling edge of SCLi 9th bit
Store Received
Data
Read Received
Data
1st to 8th bits of the received data are stored into bit
7 to bit 0 in the UiRB register
The UiRB register status is read
1st to 7th bits of the received data are stored into
bit 6 to bit 0 in the UiRB 1st to 8th bits are
register, 8th bit is stored into stored into bit 7 to bit
bit 8 in the UiRB register 0 in UiRB register ⁽³⁾
Bit 6 to bit 0 in the UiRB
register ⁽⁴⁾ are read as bit
7 to bit 1. Bit 8 in the UiRB
register is read as bit 0.
i = 0 to 2
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to 23.8 Interrupts.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set
the IR bit to “0” (interrupt not requested) after changing those bits.
• SMD2 to SMD0 bits in UiMR register
• IICM bit in UiSMR register
• IICM2 bit in UiSMR2 register
• CKPH bit in UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled).
3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)
4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)
5. See Figure 15.26 STSPSEL Bit Functions.
6. See Figure 15.24 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to “1” (cause of interrupt: UART0 bus collision detection).
When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to “1” (cause of interrupt: UART1 bus collision detection).
Rev.2.00 Nov 28, 2005 page 178 of 378
REJ09B0124-0200