M16C6NK Datasheet, PDF (111/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
10. Interrupt
Priority level of each interrupt
INT1
Level 0
(initial value)
Highest
Timer B2
Timer B0, SI/O6 ⁽²⁾
Timer A3, INT6 ⁽²⁾
Timer A1
UART1 Reception, ACK1
UART0 Reception, ACK0
UART2 Reception, ACK2
INT2
INT0
Timer B1, INT8 ⁽²⁾
Timer A4
Timer A2, INT7 ⁽²⁾
Timer A0
UART1 Transmission, NACK1
UART0 Transmission, NACK0
A/D Conversion, Key Input ⁽¹⁾
DMA1
UART2 Bus Collision Detection
Priority of peripheral function interrupts
(if priority levels are same)
CAN1 Successful Reception, SI/O4, INT5
Timer B4, UART1 Bus Collision Detection
INT3
CAN0 Successful Reception
UART2 Transmission, NACK2
CAN0/1 Error (, Key Input) ⁽¹⁾
DMA0
CAN1 Successful Transmission, SI/O3, INT4
Timer B3, UART0 Bus Collision Detection
Timer B5, SI/O5 (2)
CAN0 Successful Transmission
CAN0/1 Wake-up
IPL
I Flag
Address Match
Lowest
Interrupt request level resolution output to clock generating circuit
(Figure 8.1 Clock Generating Circuit)
Interrupt request accepted
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
DBC
NMI
NOTES:
1. If the PCLK6 bit in the PCLKR register is set to "1", the priority level of key input interrupt can be changed.
2. The SI/O5, SI/O6 and INT6 to INT8 registers are only in the 128-pin version.
Figure 10.10 Interrupts Priority Select Circuit
Rev.2.00 Nov 28, 2005 page 93 of 378
REJ09B0124-0200