M16C6NK Datasheet, PDF (215/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
SI/Oi Control Register (i = 3 to 6) ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
S4C
S5C ⁽⁶⁾
S6C ⁽⁶⁾
Address
01E2h
01E6h
01EAh
01D8h
After Reset
01000000b
01000000b
01000000b
01000000b
Bit
Symbol
Bit Name
Description
RW
b1 b0
SMi0
Internal Synchronous
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
RW
Clock Select Bit ⁽⁷⁾
SMi1
1 0 : Selecting f32SIO
1 1 : Do not set a value
RW
SMi2
SOUTi Output Disable
Bit ⁽⁴⁾
0 : SOUTi output
1 : SOUTi output disabled (high-impedance)
RW
SMi3
S I/Oi Port Select Bit ⁽⁵⁾
0 : Input/output port
1 : SOUTi output, CLKi function
RW
0 : Transmit data is output at falling edge of
transfer clock and receive data is input
SMi4 CLK Polarity Select Bit
at rising edge
1 : Transmit data is output at rising edge of
RW
transfer clock and receive data is input
at falling edge
SMi5
Transfer Direction Select 0 : LSB first
Bit
1 : MSB first
RW
Synchronous Clock
SMi6 _{Select Bit}
0 : External clock ⁽²⁾
1 : Internal clock ⁽³⁾
RW
Effective when the SMi3 bit = 0
SMi7 SOUTi Initial Value Set Bit 0 : "L" output
RW
1 : "H" output
NOTES:
1. Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to "1"
(write enabled).
2. Set the SMi3 bit to "1" (SOUTi output, CLKi function) and the corresponding port direction bit to "0" (input mode).
3. Set the SMi3 bit to "1" (SOUTi output, CLKi function).
4. When the SM32, SM52 or SM62 bit = 1, the corresponding pin is placed in the high-impedance state regardless of
which functions of those pins are being used.
SI/O4 is effective only when the SM43 bit = 1 (SOUT4 output, CLK4 function).
5. When using SI/O4, set the SM43 bit to "1" (SOUT4 output, CLK4 function) and the corresponding port direction bit
for SOUT4 pin to "0" (input mode).
6. The S5C and S6C registers are only in the 128-pin version. When using the S5C and S6C registers, set these registers
after setting the PU37 bit in the PUR3 register to "1" (Pins P11 to P14 are usable).
7. When changing the SMi1 to SMi0 bits, set the SiBRG register.
SI/Oi Bit Rate Generator (i = 3 to 6) ^{(1) (2) (4)}
Symbol
Address
S3BRG
01E3h
b7
b0
S4BRG
01E7h
S5BRG ⁽³⁾
01EBh
S6BRG ⁽³⁾
01D9h
Description
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting Range
RW
Assuming that set value = n, SiBRG divides the count
source by n + 1
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to write to this register.
3. The S5BRG and S6BRG registers are only in the 128-pin version.
4. Write to this register after setting the SMi1 to SMi0 bits in the SiC register.
00h to FFh
WO
SI/Oi Transmit/Receive Register (i = 3 to 6) ^{(1) (2)}
Symbol
Address
After Reset
b7
b0
S3TRR
01E0h
Indeterminate
S4TRR
01E4h
Indeterminate
S5TRR ⁽³⁾
01E8h
Indeterminate
S6TRR ⁽³⁾
01D6h
Indeterminate
Description
RW
Transmission/reception starts by writing transmit data to this register.
After transmission/reception finishes, reception data can be read by reading this register.
RW
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. To receive data, set the corresponding port direction bit for SINi to "0" (input mode).
3. The S5TRR and S6TRR registers are only in the 128-pin version.
Figure 15.37 S3C to S6C Registers, S3BRG to S6BRG Registers, and S3TRR to S6TRR Registers
Rev.2.00 Nov 28, 2005 page 197 of 378
REJ09B0124-0200