M16C6NK Datasheet, PDF (360/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
23. Usage Precaution
23.5 Power Control
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• When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.
• Set the MR0 bit in the TAiMR register (i = 0 to 4) to “0” (pulse is not output) to use the timer A to exit stop
mode.
• In the main clock oscillation or low power dissipation mode, set the CM02 bit in the CM0 register to “0” (do
not stop peripheral function clock in wait mode) before shifting to stop mode.
• When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not execute any
instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the
DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT
instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue roadstead
the instructions following WAIT, and depending on timing, some of these may execute before the
microcomputer enters wait mode.
Program example when entering wait mode
Program Example:
JMP.B L1
L1:
FSET I
WAIT
NOP
NOP
NOP
NOP
; Insert JMP.B instruction before WAIT instruction
;
; Enter wait mode
; More than 4 NOP instructions
• When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which
sets the CM10 bit in the CM1 register to “1”, and then insert at least 4 NOP instructions. When entering
stop mode, the instruction queue reads ahead the instructions following the instruction which sets the
CM10 bit to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop
mode or before the interrupt routine for returning from stop mode.
Program example when entering stop mode
Program Example:
L2:
FSET
BSET
JMP.B
NOP
NOP
NOP
NOP
I
CM10
L2
; Enter stop mode
; Insert JMP.B instruction
; More than 4 NOP instructions
• Wait for main clock oscillation stabilization time, before switching the clock source for CPU clock to the
main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
Rev.2.00 Nov 28, 2005 page 342 of 378
REJ09B0124-0200